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1 128mb, 64mb, 32mb q-flash memory ?2002, micron technology, inc. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 128mb, 64mb, 32mb q-flash memory ? products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. q-flash tm memory MT28F128J3 ? , mt28f640j3, mt28f320j3 ? features ? x8/x16 organization one hundred twenty-eight 128kb erase blocks (128mb) sixty-four 128kb erase blocks (64mb) thirty-two 128kb erase blocks (32mb) v cc , v cc q, and v pen voltages: 2.7v to 3.6v v cc operation 2.7v to 3.6v or 4.5v to 5.5v* v cc q operation 2.7v to 3.6v, or 5v v pen application programming interface asynchronous page mode reads: 150ns/25ns read access time (128mb) 120ns/25ns read access time (64mb) 110ns/25ns read access time (32mb) enhanced data protection feature with v pen = v ss flexible sector locking sector erase/program lockout during power transition security otp block feature permanent block locking ( contact factory for availability) industry-standard pinout inputs and outputs are fully ttl-compatible common flash interface (cfi) and scalable command set automatic write and erase algorithm 4.7s-per-byte effective programming time using write buffer 128-bit protection register 64-bit unique device identifier 64-bit user-programmable otp cells 100,000 erase cycles per block automatic suspend options: block erase suspend-to-read block erase suspend-to-program program suspend-to-read note: MT28F128J3, and mt28f320j3 are preliminary status. ? mt28f640j3 is production status. options marking timing 150ns (128mb) -15 120ns (64mb) -12 110ns (32mb) -11 operating temperature range commercial temperature (0oc to +85oc) none extended temperature (-40oc to +85oc) e t v cc q option* 2.7v?3.6v none 4.5v?5.5v f packages 56-pin tsop type i rg 64-ball fbga (1.0mm pitch) fs part number example: mt28f640j3rg-12 et *contact factory for availability of the mt28f320j3 and mt28f640j3. 56-pin tsop type i 64-ball fbga
2 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory general description the MT28F128J3 is a nonvolatile, electrically block- erasable (flash), programmable memory containing 134,217,728 bits organized as 16,777,218 bytes (8 bits) or 8,388,608 words (16 bits). this 128mb device is orga- nized as one hundred twenty-eight 128kb erase blocks. the mt28f640j3 contains 67,108,864 bits organized as 8,388,608 bytes (8 bits) or 4,194,304 words (16 bits). this 64mb device is organized as sixty-four 128kb erase blocks. similarly, the mt28f320j3 contains 33,554,432 bits organized as 4,194,304 bytes (8 bits) or 2,097,152 words (16 bits). this 32mb device is organized as thirty-two 128kb erase blocks. these three devices feature in-system block lock- ing. they also have common flash interface (cfi) that permits software algorithms to be used for entire fami- lies of devices. the software is device-independent, jedec id-independent with forward and backward compatibility. additionally, the scalable command set (scs) al- lows a single, simple software driver in all host systems to work with all scs-compliant flash memory devices. the scs provides the fastest system/device data trans- fer rates and minimizes the device and system-level implementation costs. to optimize the processor-memory interface, the device accommodates v pen , which is switchable during block erase, program, or lock bit configuration, or hardwired to v cc , depending on the application. v pen is treated as an input pin to enable erasing, program- ming, and block locking. when v pen is lower than the v cc lockout voltage (v lko ), all program functions are disabled. block erase suspend mode enables the user to stop block erase to read data from or program data to any other blocks. similarly, program suspend mode enables the user to suspend programming to read data or execute code from any unsuspended blocks. v pen serves as an input with 2.7v, 3.3v, or 5v for application programming. v pen in this q-flash ? family can provide data protection when connected to ground. this pin also enables program or erase lockout during power transition. micron?s even-sectored q-flash devices offer indi- vidual block locking that can lock and unlock a block using the sector lock bits command sequence. status (sts) is a logic signal output that gives an additional indicator of the internal state machine (ism) activity by providing a hardware signal of both status and status masking. this status indicator minimizes central processing unit (cpu) overhead and system power consumption. in the default mode, sts acts as an ry/by# pin. when low, sts indicates that the ism is performing a block erase, program, or lock bit con- figuration. when high, sts indicates that the ism is ready for a new command. three chip enable (ce) pins are used for enabling and disabling the device by activating the device?s control logic, input buffer, decoders, and sense amplifiers. byte# enables selecting x8 or x16 reads/writes to the device. byte# at logic low selects an 8-bit mode with address a0 selecting between the low byte and the high byte. byte# at logic high enables 16-bit operation. rp# is used to reset the device. when the device is disabled and rp# is at v cc , the standby mode is en- abled. a reset time ( t rwh) is required after rp# switches high until outputs are valid. likewise, the device has a wake time ( t rs) from rp# high until writes to the command user interface (cui) are rec- ognized. when rp# is at gnd, it provides write protec- tion, resets the ism, and clears the status register. a variant of the mt28f320j3 also supports the new security block lock feature for additional code security. this feature provides an otp function for locking the top two blocks, the bottom two blocks, or the entire device. (contact factory for availability.)
3 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory pin /ball assignment (top view) 56-pin tsop type i a22 ce1 a21 a20 a19 a18 a17 a16 v cc a15 a14 a13 a12 ce0 v pen rp# a11 a10 a9 a8 v ss a7 a6 a5 a4 a3 a2 a1 nc we# oe# sts dq15 dq7 dq14 dq6 v ss dq13 dq5 dq12 dq4 v cc q v ss dq11 dq3 dq10 dq2 v cc dq9 dq1 dq8 dq0 a0 byte# a23 ce2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 note: 1. a22 only exists on the 64mb and 128mb devices. on the 32mb, this pin/ball is a no connect (nc). 2. a23 only exists on the 128mb device. on the 32mb and 64mb, this pin/ball is a no connect (nc). 3. the # symbol indicates signal is active low. a b c d e f g h 1 2 3 4 5 6 7 8 top view (ball down) v pen ce0 a12 rp# dq3 dq11 v cc q v ss a8 a9 a10 a11 dq9 dq10 dq2 v cc a1 a2 a3 a4 dq8 byte# a23 ce2 v cc dnu dnu dnu dnu dnu dq6 v ss a18 a19 a20 a16 dq15 dnu dq14 dq7 a22 ce1 a21 a17 sts oe# we# nc a13 a14 a15 dnu dq4 dq12 dq5 dq13 a6 v ss a7 a5 dq1 dq0 a0 dnu 64-ball fbga device marking due to the size of the package, micron?s standard part number is not printed on the top of each device. instead, an abbreviated device mark comprised of a table 1 cross reference for abbreviated device marks product engineeri ng qualified part number marking sample sample mt28f320j3fs-11 fw201 fx201 fq201 mt28f320j3fs-11 et fw207 fx207 fq207 mt28f640j3fs-12 fw202 fx202 fq202 mt28f640j3fs-12 et fw209 fx209 fq209 MT28F128J3fs-15 fw203 fx203 fq203 MT28F128J3fs-15 et fw501 fx501 fq501 five-digit alphanumeric code is used. the abbreviated device marks are cross referenced to micron part num- bers in table 1.
4 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory y - select gates sense amplifiers write/erase-bit compare and verify addr. buffer/ latch power (current) control addr. counter command execution logic i/o control logic v pp switch/ pump status register identification register y - decoder x - decoder/block erase control state machine a0?a23 oe# we# rp# v pen dq0?dq15 ce2 output buffer input buffer write buffer v cc sts 128kb memory block (0) 128kb memory block (127) 128kb memory block (1) 128kb memory block (2) 128kb memory block (125) 128kb memory block (126) query ce1 ce0 ce logic functional block diagram (128mb) y - select gates sense amplifiers write/erase-bit compare and verify addr. buffer/ latch power (current) control addr. counter command execution logic i/o control logic v pp switch/ pump status register identification register y - decoder x - decoder/block erase control state machine a0?a22 oe# we# rp# v pen dq0?dq15 ce2 output buffer input buffer write buffer v cc sts 128kb memory block (0) 128kb memory block (63) 128kb memory block (1) 128kb memory block (2) 128kb memory block (61) 128kb memory block (62) query ce1 ce0 ce logic functional block diagram (64mb)
5 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory y - select gates sense amplifiers write/erase-bit compare and verify addr. buffer/ latch power (current) control addr. counter command execution logic i/o control logic v pp switch/ pump status register identification register y - decoder x - decoder/block erase control state machine a0?a21 oe# we# rp# v pen dq0?dq15 ce2 output buffer input buffer write buffer v cc sts 128kb memory block (0) 128kb memory block (31) 128kb memory block (1) 128kb memory block (2) 128kb memory block (29) 128kb memory block (30) query ce1 ce0 ce logic functional block diagram (32mb)
6 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory pin/ball descriptions 56-pin tsop 64- ball fbga numbers numbers symbol type description 55 g8 we# input w rite enable: determines if a given cycle is a write cycle. if we# is low, the cycle is either a write to the command execution logic (cel) or to the memory array. addresses and data are latched on the rising edge of the we# pulse. 14, 2, 29 b4, b8, h1 ce0, ce1, input chip enable: three ce pins enable the use of multiple ce2 flash devices in the system without requiring additional logic. the device can be configured to use a single ce signal by tying ce1 and ce2 to ground and then using ce0 as ce. device selection occurs with the first edge of ce0, ce1, or ce2 (cex) that enables the device. device deselection occurs with the first edge of cex that disables the device (see table 2). 16 d4 rp# input reset/power-down: when low, rp# clears the status register, sets the ism to the array read mode, and places the device in deep power-down mode. all inputs, including cex, are ?don?t care,? and all outputs are high-z. rp# must be held at v ih during all other modes of operation. 54 f8 oe# input output enables: enables data ouput buffers when low. when oe# is high, the output buffers are disabled. 32, 28, 27, g2, a1, b1, c1, a0?a21/ input address inputs during read and write operations. a0 is 26, 25, 24, 23, d1, d2, a2, c2, (a22) only used in x8 mode. a22 (pin 1, ball a8) is only 22, 20, 19, 18, a3, b3, c3, d3, (a23) available on the 64mb and 128mb devices. a23 (pin 30, 17, 13, 12, 11, c4, a5, b5, c5, ball g1) is only available on the 128mb device. 10, 8, 7, 6, 5, 4, d7, d8, a7, b7, 3, 1, 30 c7, c8, a8, g1 31 f1 byte# input byte# low places the device in the x8 mode. byte# high places the device in the x16 mode and turns off the a0 input buffer. address a1 becomes the lowest order address in x16 mode. 15 a4 v pen input necessary voltage for erasing blocks, programming data, or configuring lock bits. typically, v pen is connected to v cc . when v pen v penlk , this pin enables hardware write protect. 33, 35, 38, 40, f2, e2, g3, e4, dq0? input/ data i/o: data output pins during any read operation 44, 46, 49, 51, e5, g5, g6, h7, dq15 output or data input pins during a write. dq8?dq15 are not 34, 36, 39, 41, e1, e3, f3, f4, used in byte mode. 45, 47, 50, 52 f5, h5, g7, e7 53 e8 sts output status: indicates the status of the ism. when configured in level mode, default mode it acts as an ry/by# pin. when configured in its pulse mode, it can pulse to indicate program and/or erase completion. tie sts to v cc q through a pull-up resistor. (continued on next page)
7 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory pin/ball descriptions (continued) 56-pin tsop 64- ball fbga numbers numbers symbol type description 43 g4 v cc q supply v cc q controls the output voltages. to obtain output voltage compatible with system data bus voltages, connect v cc q to the system supply voltage. 9, 37 h3, a6 v cc supply power supply: 2.7v to 3.6v. 21, 42, 48 b2, h4, h6 v ss supply ground. 56 h8 nc ? no connect: these may be driven or left unconnected. pin 1 and ball a8 are ncs on the 32mb device. pin 30 and ball g1 are ncs on the 32mb and 64mb devices. ? b6, c6, d5, d6, dnu ? do not use: must float to minimize noise. e6, f6, f7, h2
8 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 1 memory map table 2 chip enable truth table ce2 ce1 ce0 device v il v il v il enabled v il v il v ih disabled v il v ih v il disabled v il v ih v ih disabled v ih v il v il enabled v ih v il v ih enabled v ih v ih v il enabled v ih v ih v ih disabled note: for single-chip applications, ce2 and ce1 can be connected to gnd. 128kb block 31 128kb block 1 128kb block 0 64k-word block 63 64k-word block 31 64k-word block 1 64k-word block 0 7fffffh 7e0000h 3fffffh 3e0000h 03ffffh 020000h 01ffffh 000000h 3fffffh 3f0000h 1fffffh 1f0000h 01ffffh 010000h 00ffffh 000000h 32m b 64mb 128mb byte-wide (x8) mode word-wide (x16) mode a0?a23: 128mb a0?a22: 64mb a0?a21: 32mb a1?a23: 128mb a1?a22: 64mb a1?a21: 32mb 128kb block 63 64k-word block 127 ffffffh fe0000h 7fffffh 7f0000h 128kb block 127 memory architecture the MT28F128J3, mt28f640j3, and mt28f320j3 memory array architecture is divided into one hun- dred twenty-eight, sixty-four, or thirty-two 128kb blocks, respectively (see figure 1). the internal archi- tecture allows greater flexibility when updating data because individual code portions can be updated in- dependently of the rest of the code. high-speed page buffer. a0?a2 select data in the page buffer. asynchronous page mode, with a page size of four words or eight bytes, is supported with no addi- tional commands required. output disable the device outputs are disabled with oe# at a logic high level (v ih ). output pins dq0?dq15 are placed in high-z. standby ce0, ce1, and ce2 can disable the device (see table 2) and place it in standby mode, which substan- tially reduces device power consumption. dq0?dq15 outputs are placed in high-z, independent of oe#. if deselected during block erase, program, or lock bit con- figuration, the ism continues functioning and consum- ing active power until the operation completes. reset/power-down rp# puts the device into the reset/power-down mode when set to v il . during read, rp# low deselects the memory, places output drivers in high-z, and turns off internal cir- cuitry. rp# must be held low for a minimum of t plph. t rwh is required after return from reset mode until initial memory access outputs are valid. after this wake- up interval, normal operation is restored. the com- mand execution logic (cel) is reset to the read array mode and the status register is set to 80h. during block erase, program, or lock bit configura- tion, rp# low aborts the operation. in default mode, sts transitions low and remains low for a maximum time of t plph + t phrh, until the reset operation is complete. any memory content changes are no longer bus operation all bus cycles to and from the flash memory must conform to the standard microprocessor bus cycles. the local cpu reads and writes flash memory in- system. read information can be read from any block, query, iden- tifier codes, or status register, regardless of the v pen voltage. the device automatically resets to read array mode upon initial device power-up or after exit from reset/power-down mode. to access other read mode commands (read array, read query, read iden- tifier codes, or read status register), these commands should be issued to the cui. six control pins dictate the data flow in and out of the device: ce0, ce1, ce2, oe#, we#, and rp#. in system designs using multiple q-flash devices, ce0, ce1, and ce2 (cex) select the memory device (see table 2). to drive data out of the device and onto the i/o bus, oe# must be active and we# must be inactive (v ih ). when reading information in read array mode, the device defaults to asynchronous page mode, thus pro- viding a high data transfer rate for memory subsystems. in this state, data is internally read and stored in a
9 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory valid; the data may be partially corrupted after a pro- gram or partially changed after an erase or lock bit configuration. after rp# goes to logic high (v ih ), and after t rs, another command can be written. it is important to assert rp# during system reset. after coming out of reset, the system expects to read from the flash memory. during block erase, program, or lock bit configuration mode, automated flash memo- ries provide status information when accessed. when a cpu reset occurs with no flash memory reset, proper initialization may not occur because the flash memory may be providing status information instead of array data. micron flash memories allow proper initializa- tion following a system reset through the use of the rp# input. rp# should be controlled by the same reset# signal that resets the system cpu. read query the read query operation produces block status information, cfi id string, system interface informa- tion, device geometry information, and extended query information. read identifier codes the read identifier codes operation produces the manufacturer code, device code, and the block lock configuration codes for each block (see figure 2). the block lock configuration codes identify locked and un- locked blocks. write writing commands to the cel allows reading of de- vice data, query, identifier codes, and reading and clear- ing of the status register. in addition, when v pen = v penh , block erasure, program, and lock bit configuration can also be performed. the block erase command requires suitable com- mand data and an address within the block. the byte/ word program command requires the command and address of the location to be written to. the clear block lock bits command requires the command and any address within the device. set block lock bits command requires the command and the block to be locked. the cel does not occupy an addressable memory location. it is written to when the device is enabled and we# is low. the address and data needed to execute a command are latched on the rising edge of we# or the first edge of cex that disables the device (see table 2). standard microprocessor write timings are used. reserved for future implementation manufacturer code device code 010000h 00ffffh 000004h 000003h 000002h 000001h 000000h reserved for future implementation reserved for future implementation reserved for future implementation block 63 block 0 3fffffh 3f0003h 3f0002h 3f0000h 3effffh 1effffh 1f0003h 1f0002h 1f0000h 01ffffh 010003h 010002h 32mb 64mb 128mb block 63 lock configuration block 0 lock configuration reserved for future implementation (blocks 32 through 62) reserved for future implementation 7fffffh 7f0003h 7f0002h 7f0000h 7effffh block 127 lock configuration reserved for future implementation block 31 reserved for future implementation (blocks 2 through 30) block 1 reserved for future implementation block 1 lock configuration block 127 block 31 lock configuration (blocks 64 through 126) figure 2 device identifier code memory map note: when obtaining these identifier codes, a0 is not used in either x8 or x16 modes. data is always given on the low byte in x16 mode (upper byte contains 00h).
10 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 3 bus operations ce0, ce1, sts default mode rp# ce2 1 oe# 2 we# 2 address v pen dq 3 mode notes read array v ih enabled v il v ih xxd out high-z 4 5, 6, 7 output disable v ih enabled v ih v ih x x high-z x standby v ih disabled x x x x high-z x reset/power-down v il x x x x x high-z high-z 4 mode read identifier codes v ih enabled v il v ih see x note 8 high-z 4 figure 2 read query v ih enabled v il v ih see x note 9 high-z 4 table 7 read status (ism off) v ih enabled v il v ih xxd out read status (ism on) v ih enabled v il v ih xx dq7 d out dq15?dq8 high-z dq6?dq0 high-z write v ih enabled v ih v il xv penh d in x 7, 10, 11 note: 1. see table 2 for valid ce configurations. 2. oe# and we# should never be enabled simultaneously. 3. dq refers to dq0?dq7 if byte# is low and dq0?dq15 if byte# is high. 4. high-z is v oh with an external pull-up resistor. 5. refer to dc characteristics. when v pen v penlk , memory contents can be read, but not altered. 6. x can be v il or v ih for control and address pins, and v penlk or v penh for v pen . see dc characteristics for v penlk and v penh voltages. 7. in default mode, sts is v ol when the ism is executing internal block erase, program, or lock bit configuration algorithms. it is v oh when the ism is not busy, in block erase suspend mode (with programming inactive), program suspend mode, or reset/power-down mode. 8. see read identifier codes section for read identifier code data. 9. see read query mode command section for read query data. 10. command writes involving block erase, program, or lock bit configuration are reliably executed when v pen = v penh and v cc is within specification. 11. refer to table 4 for valid d in during a write operation.
11 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 4 micron q-flash memory command set definitions 1 command scalable bus or basic cycles first bus cycle second bus cycle command req?d set 2 oper 3 addr 4 data 5, 6 oper 3 addr 4 data 5, 6 notes* read array scs/bcs 1 w rite x ffh read identifier scs/bcs 2 write x 90h read ia id 7 codes read query scs 2 write x 98h read qa qd read status scs/bcs 2 w rite x 70h read x srd 8 register clear status scs/bcs 1 w rite x 50h register write to buffer scs/bcs > 2 w rite ba e8h write ba n 9, 10, 11 word/byte scs/bcs 2 w rite x 40h write pa pd 12, 13 program or 10h block erase scs/bcs 2 w rite ba 20h write ba d0h 11, 12 block erase, scs/bcs 1 w rite x b0h 12, 14 program suspend block erase, scs/bcs 1 w rite x d0h 12 program resume configuration scs 2 w rite x b8h write x cc set block lock bits scs 2 w rite x 60h write ba 01h clear block scs 2 w rite x 60h write x d0h 15 lock bits protection 2 write x c0h write pa pd program *notes appear on the next page. command definitions when the v pen voltage is less than v pplk , only read operations from the status register, query, identifier codes, or blocks are enabled. placing v penh on v pen en- ables block erase, program, and lock bit con- figuration operations. device operations are se- lected by writing specific commands into the cel, as seen in table 4.
12 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory note: 1. commands other than those shown in table 4 are reserved for future device implementations and should not be used. 2. the scs is also referred to as the extended command set. 3. bus operations are defined in table 3. 4. x = any valid address within the device ba = address within the block ia = identifier code address; see figure 2 and table 15 qa = query data base address pa = address of memory location to be programmed 5. id = data read from identifier codes qd = data read from query data base srd = d ata read from status register; see table 16 for a description of the status register bits pd = data to be programmed at location pa; data is latched on the rising edge of we# cc = configuration code 6. the upper byte of the data bus (dq8?dq15) during command writes is a ?don?t care? in x16 operation. 7. following the read identifier codes command, read operations access manufacturer, device, and block lock codes. see block status register section for read identifier code data. 8. if the ism is running, only dq7 is valid; dq15?dq8 and dq6?dq0 float, which places them in high-z. 9. after the write-to-buffer command is issued, check the xsr to make sure a buffer is available for writing. 10. the number of bytes/words to be written to the write buffer = n + 1, where n = byte/word count argument. count ranges on this device for byte mode are n = 00h to n = 1fh and for word mode, n = 0000h to n = 000fh. the third and consecutive bus cycles, as determined by n , are for writing data into the write buffer. the confirm command (d0h) is expected after exactly n + 1 write cycles; any other command at that point in the sequence aborts the write-to- buffer operation. please see figure 4, write-to-buffer flowchart, for additional information. 11. the write-to-buffer or erase operation does not begin until a confirm command (d0h) is issued. 12. attempts to issue a block erase or program to a locked block while rp# = v ih will fail. 13. either 40h or 10h is recognized by the ism as the byte/word program setup. 14. program suspend can be issued after either the write-to-buffer or word/byte program operation is initiated. 15. the clear block lock bits operation simultaneously clears all block lock bits.
13 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 5 summary of query structure output as a function of device and mode query data with maximum device bus query data with byte device query start location in width addressing addressing type/ maximum device bus hex hex ascii hex hex ascii mode width addresses offset code value offset code value x16 device 10h 10 0051 q 20 51 q x16 mode 11 0052 r 21 00 null 12 0059 y 22 52 r x16 device 20 51 q x8 mode n/a 1 n/a 1 21 51 q 22 52 r read array command the device defaults to read array mode upon initial device power-up and after exiting reset/power-down mode. the read configuration register defaults to asyn- chronous read page mode. until another command is written, the read array command also causes the device to enter read array mode. when the ism has started a block erase, program, or lock bit configura- tion, the device does not recognize the read array command until the ism completes its operation, un- less the ism is suspended via an erase or program suspend command. the read array command functions independently of the v pen voltage. read query mode command this section is related to the definition of the data structure or ?data base? returned by the cfi query command. system software should retain this struc- ture to gain critical information such as block size, density, x8/x16, and electrical specifications. when this information has been obtained, the software knows which command sets to use to enable flash writes or block erases, and otherwise control the flash component. query structure output the query ?data base? enables system software to obtain information about controlling the flash compo- nent. the device?s cfi-compliant interface allows the host system to access query data. query data are al- ways located on the lowest-order data outputs (dq0? dq7) only. the numerical offset value is the address relative to the maximum bus width supported by the device. on this family of devices, the query table de- vice starting address is a 10h, which is a word address for x16 devices. for a x16 organization, the first two bytes of the query structure, ?q? and ?r? in ascii, appear on the low byte at word addresses 10h and 11h. this cfi- compliant device outputs 00h data on upper bytes, thus making the device output ascii ?q? on the low byte (dq7?dq0) and 00h on the high byte (dq15? dq8). at query addresses containing two or more bytes of information, the least significant data byte is located at the lower address, and the most significant data byte is located at the higher address. this is summa- rized in table 5. a more detailed example is provided in table 6. note: 1. the system must drive the lowest-order addresses to access all the device?s array data when the device is configured in x8 mode. therefore, word addressing where these lower addresses are not toggled by the system is ?not applicable? for x8-configured devices.
14 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 6 example of query structure output of a x16- and x8-capable device word addressing byte addressing offset hex code value offset hex code value a16?a1 dq15?dq0 a7?a0 dq7?dq0 0010h 0051 q 20h 51 q 0011h 0052 r 21h 51 q 0012h 0059 y 22h 52 r 0013h p_id lo prvendor 23h 52 r 0014h p_id hi id # 24h 59 y 0015h p lo prvendor 25h 59 y 0016h p hi tbladr 26h p_id lo prvendor 0017h a_id lo altvendor 27h p_id lo prvendor 0018h a_id hi id # 28h p_id hi id # ... ... ... ... ... ... query structure overview the query command makes the flash component display the cfi query structure or data base. the struc- ture subsections and address locations are outlined in table 7. table 7 query structure 1 offset subsection name description 00h manufacturer compatibility code 01h device code (ba+2)h 2 block status register block-specific information 04?0fh reserved reserved for vendor-specific information 10h cfi query identification string reserved for vendor-specific information 1bh system interface information command set id and vendor data offset 27h device geometry definition flash device layout p 3 primary extended query table vendor-defined additional information specific to the primary vendor algorithm note: 1. refer to the query structure output section and offset 28h for the detailed definition of offset address as a function of device bus width and mode. 2. ba = block address beginning location (i.e., 020000h is block two?s beginning location when the block size is 64k-word). 3. offset 15 defines ?p,? which points to the primary extended query table.
15 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 9 cfi identification offset length description a ddress hex value code 10h 3 query-unique ascii string ?qry? 10h 51 q 11h 52 r 12h 59 y 13h 2 primary vendor command set and control interface id 13h 01 code. 16-bit id code for vendor-specified algorithms 14h 00 15h 2 extended query table primary algorithm address 15h 31 16h 00 17h 2 alternate vendor command set and control interface id 17h 00 code; 0000h means no second vendor-specified 18h 00 algorithm exists 19h 2 secondary algorithm extended query table address; 19h 00 0000h means none exists 1ah 00 table 8 block status register offset length description address 1 value (ba+2)h 1 1 block lock status register (ba +2)h 00 or 01 bsr0 block lock status 0 = unlocked (ba +2)h (bit 0) 0 or 1 1 = locked bsr1?7 reserved for future use (ba +2)h (bit 2?7) 0 cfi query identification string the cfi query identification string verifies whether the component supports the cfi specification. addi- tionally, it indicates the specification version and sup- ported vendor-specified command set(s). note: 1. ba = the beginning location of a block address (i.e., 010000h is block one?s (64k-word) beginning location in word mode).
16 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory system interface information table 10 provides useful information about opti- mizing system interface software. table 10 system interface information offset length description a ddress hex value code 1bh 1 v cc logic supply minimum program/erase voltage bits 0?3 bcd 100mv 1bh 27 2.7v bits 4?7 bcd volts 1ch 1 v cc logic supply maximum program/erase voltage bits 0?3 bcd 100mv 1ch 36 3.6v bits 4?7 bcd volts 1dh 1 v pp [programming] supply minimum program/erase voltage bits 0?3 bcd 100mv 1dh 00 0.0v bits 4?7 hex volts 1eh 1 v pp [programming] supply maximum program/erase voltage bits 0?3 bcd 100mv 1eh 00 0.0v bits 4?7 hex volts 1fh 1 ?n? such that typical single word program 1fh 07 128s timeout = 2 n s 20h 1 ?n? such that typical max. buffer write timeout = 2 n s 20h 07 128s 21h 1 ?n? such that typical block erase timeout = 2 n ms 21h 0a 1s 22h 1 ?n? such that typical full chip erase timeout = 2 n ms 22h 00 n/a 23h 1 ?n? such that maximum word program timeout = 2 n 23h 04 2ms times typical 24h 1 ?n? such that maximum buffer write timeout = 2 n 24h 04 2ms times typical 25h 1 ?n? such that maximum block erase timeout = 2 n 25h 04 16s times typical 26h 1 ?n? such that maximum chip erase timeout = 2 n 26h 00 n/a times typical
17 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory device geometry definition tables 11a and 11b provide important details about the device geometry. table 11a device geometry definitions offset length description code (see table below) 27h 1 ?n? such that device size = 2 n in number of bytes 27h 28h 2 flash device interface: x8 async, x16 async, x8/x16 async; 28h 02 x8/x16 28:00 29:00, 28:01 29:00, 28:02 29:00 29h 00 2ah 2 ?n? such that maximum number of bytes in write 2ah 05 32 buffer = 2 n 2bh 00 2ch 1 number of erase block regions within device: 2ch 01 1 1. x = 0 means no erase blocking; the device erases in ?bulk? 2. x specifies the number of device or partition regions with one or more contiguous same-size erase blocks 3. symmetrically blocked partitions have one blocking region 4. partition size = (total blocks) x (individual block size) 2dh 4 erase block region 1 information 2dh bits 0?15 = y; y + 1 = number of identical-size erase blocks 2eh bits 16?31 = z; region erase block(s) size are z x 256 bytes 2fh 30h table 11b device geometry definition codes address 32mb 64mb 128mb 27h 16 17 18 28h 02 02 02 29h 00 00 00 2ah 05 05 05 2bh 00 00 00 2ch 01 01 01 2dh 1f 3f 7f 2eh 00 00 00 2fh 00 00 00 30h 02 02 02
18 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory note: 1. future devices may not support the described ?legacy lock/unlock? function. on these devices, bit 3 would have a value of ?0.? primary vendor-specific extended query table table 12 includes information about optional flash features and commands and other similar infor- mation. table 12 primary vendor-specific extended query offset 1 description a ddress hex value p = 31h (optional flash features and commands) code (p+0)h primary ext ended query table 31h 50 p (p+1)h unique ascii string, pri 32h 52 r (p+2)h 33h 49 i (p+3)h major version number, ascii 34h 31 1 (p+4)h minor version number, ascii 35h 31 1 (p+5)h optional feature and command support (1 = yes, 0 = no) bits 9?31 36h 0a (p+6)h are reserved; undefined bits are ?0.? if bit 31 is ?1,? then another 37h 00 (p+7)h 31-bit field of optional features follows at the end of the bit 30 38h 00 (p+8)h field. 39h 0 bit 0 chip erase supported = no = 0 bit 1 suspend erase supported = yes = 1 bit 2 suspend program supported = yes = 1 bit 3 legacy lock/unlock supported = yes = 1 1 bit 4 queued erase supported = no = 0 bit 5 instant individual block locking supported = no = 0 bit 6 protection bits supported = yes = 1 bit 7 page mode read supported = yes = 1 bit 8 synchronous read supported = no = 0 (p+9)h supported functions after suspend: read array, status, query 3ah 01 other supported operations: bits 1?7 reserved; undefined bits are ?0? bit 0 program supported after erase suspend = yes = 1 (p+a)h block status register mask 3bh 01 (p+b)h bits 2?15 reserved; undefined bits are ?0? 3ch 00 bit 0 block lock bit status register active = yes = 1 bit 1 block lock down bit status active = no = 0 (p+c)h v cc logic supply highest-performance program/erase voltage bits 0?3 bcd value in 100mv 3dh 33 3.3v bits 4?7 bcd value in volts (p+d)h v pp optimum program/erase supply voltage bits 0?3 bcd value in 100mv 3eh 00 0.0v bits 4?7 hex value in volts
19 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 13 protection register information offset 1 description a ddress hex value p = 31h (optional flash features and commands) code (p+e)h number of protection register fields in jedec id space. ?00h? 3fh 01 01 indicates that 256 protection bytes are available. (p+f)h protection field 1: protection description 40h 00 00h (p+10)h this field describes user-available, one-time programmable (otp) (p+11)h protection register bytes. some are preprogrammed with device- (p+12)h unique serial numbers; others are user-programmable. bits 0?15 point to the protection register lock byte, the section?s first byte. the following bytes are factory-preprogrammed and user- programmable. bits 0?7 lock/bytes jedec-plane physical low address bits 8?15 lock/bytes jedec-plane physical high address bits 16?23 ?n? such that 2 n = factory preprogrammed bytes bits 24?31 ?n? such that 2 n = user-programmable bytes table 14 burst read information offset 1 description a ddress hex value p = 31h (optional flash features and commands) code (p+13)h page mode read capability 44h 03 8 byte bits 0?7 = ?n? such that 2 n hex value represents the number of read page bytes. see offset 28h for device word width to determine page mode data output width. 00h indicates no read page buffer. (p+14)h number of synchronous mode read configuration fields 45h 00 that follow. 00h indicates no burst capability. (p+15)h reserved for future use. 46h note: 1. the variable ?p? is a pointer which is defined at cfi offset 15h.
20 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 15 identifier codes code address 1 data manufacturer compatibility code 00000h (00) 89 device code ? 32mb 00001h (00) 16 ? 64mb 00001h (00) 17 ? 128mb 00001h (00) 18 block lock configuration x0002h 2 ? block is unlocked dq0 = 0 ? block is locked dq0 = 1 ? reserved for future use dq1?dq7 note: 1. a0 is not used in either x8 or x16 modes when obtaining the identifier codes. the lowest-order address line is a1. data is always presented on the low byte in x16 mode (upper byte contains 00h). 2. x selects the specific block?s lock configuration code. see figure 2 for the device identifier code memory map. read identifier codes command writing the read identifier codes command initiates the identifier code operation. following the writing of the command, read cycles from ad- dresses shown in figure 2 retrieve the manufacturer, device, and block lock configuration codes (see table 15 for identifier code values). page mode reads are not supported in this read mode. to terminate the op- eration, write another valid command. the read identifier codes command functions indepen- dently of the v pen voltage. this command is valid only when the ism is off or the device is suspended. see table 15 for read identifier codes. read status register command the status register may be read at any time by writ- ing the read status register command to deter- mine the successful completion of programming, block erasure, or lock bit configuration. after writing this com- mand, all subsequent read operations output data from the status register until another valid command is written. page mode reads are not supported in this read mode. the status register contents are latched on the falling edge of oe# or the first edge of cex that enables the device (see table 2). to update the status register latch, oe# must toggle to v ih or the device must be disabled before further reads. the read status register command functions independently of the v pen voltage. during a program, block erase, set block lock bits, or clear block lock bits command sequence, only sr7 is valid until the ism completes or suspends the operation. device i/o pins dq0?dq6 and dq8? dq15 are placed in high-z. when the operation com- pletes or suspends (check status register bit 7), all con- tents of the status register are valid during a read.
21 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory high-z when status register bits notes busy? no sr7 = write state machine status (isms) check sts or sr7 to determine block 1 = ready erase, program, or lock bit 0 = busy configuration completion. sr6?sr0 are not driven while sr7 = 0. yes sr6 = erase suspend status (ess) 1 = block erase suspended 0 = block erase in progress/completed yes sr5 = erase and clear lock bits status (eclbs) if both sr5 and sr4 are ?1s? after a 1 = error in block erasure or clear lock bits block erase or lock bit configuration 0 = successful block erase or clear lock bits attempt, an improper command sequence was entered. yes sr4 = program and set lock bit status (pslbs) 1 = error in programming or setting block lock bits 0 = successful program or set block lock bits yes sr3 = programming voltage status (v pens ) sr3 does not provide a continuous 1 = low programming voltage detected, programming voltage level indication. operation aborted the ism interrogates and indicates the 0 = programming voltage ok programming voltage level only after block erase, program, set block lock bits, or clear block lock bits command sequences. yes sr2 = program suspend status (pss) 1 = program suspended 0 = program in progress/completed yes sr1 = device protect status (dps) sr1 does not provide a continuous 1 = block lock bit detected, operation aborted indication of block lock bit values. the 0 = unlock ism interrogates the block lock bits only after block erase, program, or lock bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock bit is set. read the block lock configuration codes using the read identifier codes command to determine block lock bit status. sr0 is reserved for future use and should be masked when polling the status register. yes sr0 = reserved for future enhancements table 16 status register definitions isms ess eclbs pslbs v pens pss dps r 76543210
22 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 17 extended status register definitions (xsr) wbs reserved 7 6?0 clear status register command the ism sets the status register bits sr5, sr4, sr3, and sr1 to ?1s.? these bits, which indicate various failure conditions, can only be reset by the clear sta- tus register command. allowing system software to reset these bits can perform several operations (such as cumulatively erasing or locking multiple blocks or writing several bytes in sequence). to determine if an error occurred during the sequence, the status register may be polled. to clear the status register, the clear status register command (50h) is written. the clear status register command functions inde- pendently of the applied v pen voltage and is only valid when the ism is off or the device is suspended. block erase command the block erase command is a two-cycle com- mand that erases one block. first, a block erase setup is written, followed by a block erase confirm. this com- mand sequence requires an appropriate address within the block to be erased. the ism handles all block pre- conditioning, erase, and verify. time t wb after the two- cycle block erase sequence is written, the device auto- matically outputs status register data when read. the cpu can detect block erase completion by analyzing the output of the sts pin or status register bit sr7. toggle oe# or cex to update the status register. upon block erase completion, status register bit sr5 should be checked to detect any block erase error. when an error is detected, the status register should be cleared before system software attempts corrective actions. the cel remains in read status register mode until a new command is issued. this two-step setup command sequence ensures that block contents are not acciden- tally erased. an invalid block erase command sequence results in status register bits sr4 and sr5 being set to ?1.? also, reliable block erasure can only occur when v cc is valid and v pen = v penh . note that sr3 and sr5 are set to ?1? if block erase is attempted while v pen v penlk . successful block erase requires that the corresponding block lock bit be cleared. similarly, sr1 and sr5 are set to ?1? if block erase is attempted when the correspond- ing block lock bit is set. block erase suspend command the block erase suspend command allows block erase interruption in order to read or program data in another block of memory. writing the block erase suspend command immediately after start- ing the block erase process requests that the ism sus- pend the block erase sequence at an appropriate point in the algorithm. when reading after the block erase suspend command is written, the device outputs sta- tus register data. polling status register bit sr7, fol- lowed by sr6, shows when the block erase opera- tion has been suspended. in the default mode, sts also transitions to v oh . t les defines the block erase suspend latency. at this point, a read array com- mand can be written to read data from blocks other than that which is suspended. during erase suspend to program data in other blocks, a program command sequence can also be issued. during a program op- eration with block erase suspended, status register bit sr7 returns to ?0? and sts output (in default mode) transitions to v ol . however, sr6 remains ?1? to indicate block erase suspend status. using the program sus- pend command, a program operation can also be suspended. resuming a suspended programming op- eration by issuing the program resume command high-z when status register bits notes busy? no xsr7 = write buffer status (wbs) after a buffer write command, 1 = write buffer available xsr7 = 1 indicates that a write buffer is 0 = write buffer not available available. yes xsr6?xsr0 = reserved for future sr6?sr0 are reserved for future use enhancements and should be masked when polling the status register.
23 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory enables the suspended programming operation to con- tinue. to resume the suspended erase, the user must wait for the programming operation to complete be- fore issuing the block erase resume command. while block erase is suspended, the only other valid commands are read query, read status regis- ter, clear status register, configure, and block erase resume. after a block erase resume command to the flash memory is completed, the ism continues the block erase process. status register bits sr6 and sr7 automatically clear and sts (in default mode) returns to v ol . after the erase resume com- mand is completed, the device automatically outputs status register data when read. v pen must remain at v penh (the same v pen level used for block erase) during block erase suspension. block erase cannot resume during block erase suspend until program opera- tions are complete. write-to-buffer command the write-to-buffer command sequence is initiated to program the flash device via the write buffer. a buffer can be loaded with a variable number of bytes, up to the buffer size, before writing to the flash device. first, the write-to-buffer setup command is issued, along with the block address (see figure 4). then, the extended status register (xsr; see table 17) informa- tion is loaded and xsr7 indicates ?buffer available? status. if xsr7 = 0, the write buffer is not available. to retry, issue the write-to-buffer setup command with the block address and continue monitoring xsr7 until xsr7 = 1. when xsr7 transitions to ?1,? the buffer is ready for loading new data. then the part is given a word/byte count with the block address. on the next write, a device start address is given, along with the write buffer data. depending on the count, subsequent writes provide additional device addresses and data. all subsequent addresses must lie within the start ad- dress plus the count. the device internally programs many flash cells in parallel. due to this parallel programming, maximum programming performance and lower power are ob- tained by aligning the start address at the beginning of a write buffer boundary (i.e., a0?a4 of the start address = 0). when the final buffer data is given, a write con- firm command is issued, thus programming the ism to begin copying the buffer data to the flash array. if the device receives a command other than write con- firm, an invalid command/sequence error is gener- ated and status register bits sr5 and sr4 are set to ?1.? for additional buffer writes, issue another write- to-buffer setup command and check xsr7. if an error occurs during a write, the device stops writing, and status register bit sr4 is set to a ?1? to indicate a program failure. the ism only detects errors for ?1s? that do not successfully program to ?0s.? when a program error is detected, the status register should be cleared. note that the device does not accept any more write-to-buffer commands any time sr4 and/ or sr5 is set. in addition, if the user attempts to pro- gram past an erase block boundary with a write-to- buffer command, the device aborts the write-to- buffer operation and generates an invalid command/ sequence error, and status register bits sr5 and sr4 are set to ?1.? reliable buffered writes can only occur when v pen = v penh . if a buffered write is attempted while v pen v penlk , status register bits sr4 and sr3 are set to ?1.? buffered write attempts with invalid v cc and v pen voltages produce spurious results and should not be attempted. finally, the corresponding block lock bit should be reset for successful programming. when a buffered write is attempted while the correspond- ing block lock bit is set, sr1 and sr4 are set to ?1.? byte/word program commands a two-cycle command sequence executes a byte/ word program setup. this program setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). next, the ism takes over to internally control the programming and program verify algorithms. when the program sequence is written, the device automatically outputs status register data when read (see figure 5). the cpu can detect the completion of the program event by analyzing the sts pin or status register bit sr7. upon program completion, status register bit sr4 should be checked. the status register should be cleared if a program error is detected. the ism only detects errors for ?1s? that do not successfully program to ?0s.? the cel remains in read status register mode until it receives another command. reliable byte/word programs can only occur when v cc and v pen are valid. status register bits sr4 and sr3 are set to ?1? if a byte/word program is attempted while v pen v penlk . the corresponding block lock bit should be cleared for successful byte/word programs. if byte/ word is attempted while the corresponding block lock bit is set, sr1 and sr4 are set to ?1.? program suspend command the program suspend command enables pro- gram interruption to read data in other flash memory locations. after starting the programming process, writ-
24 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory ing the program suspend command requests that the ism suspend the program sequence at a predeter- mined point in the algorithm. when the program suspend command is written, the device continues to output status register data when read. polling status register bit sr7 can determine when the programming operation has been suspended. when sr7 = 1, sr2 is also set to ?1? to indicate that the device is in the pro- gram suspend mode. sts in ry/by# level mode also transitions to v oh . note that t lps defines the program suspend latency. hence, a read array command can be written to read data from unsuspended locations. while pro- gramming is suspended, the only other valid com- mands are read query, read status register, clear status register, configure, and program resume. when the program resume command is written, the ism continues the program- ming process. status register bits sr2 and sr7 auto- matically clear and sts in ry/by# mode returns to v ol . after the program resume command is written, the device automatically outputs status register data when read. v pen must remain at v penh and v cc must remain at valid v cc levels (the same v pen and v cc levels used for programming) while in program suspend mode. refer to figure 6 (program suspend/resume flowchart). set read configuration command q-flash memory does not support the set read configuration command. the devices default to the asynchronous page mode. if this command is given, the operation of the device will not be affected. read configuration micron?s q-flash devices support both asynchro- nous page mode and standard word/byte reads with- out configuration requirement. status register and identifier only support standard word/byte single read operations. sts configuration command using the configuration command, the sts pin can be configured to different states. once configured, the sts pin remains in that configuration until another configuration command is issued, rp# is asserted low, or the device is powered down. initially, the sts pin defaults to ry/by# operation where ry/by# goes low to indicate that the state machine is busy. when high, ry/by# indicates that either the state machine is ready for a new operation or it is suspended. table 18, con- figuration coding definitions, shows the possible sts configurations. to change the sts pin to other modes, the configuration command is given, followed by the desired configuration code. the three alternate configurations are all pulse modes and may be used as a system interrupt. with these configurations, bit 0 controls erase complete interrupt pulse, and bit 1 con- trols program complete interrupt pulse. providing the 00h configuration code with the configuration command resets the sts pin to the default ry/by# level mode. table 18 describes possible configurations and usage. the configuration command can only be given when the device is not busy or suspended. when configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250ns. check sr7 for device status. an invalid configuration code results in status register bits sr4 and sr5 being set to ?1.?
25 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory set block lock bits command a flexible block locking and unlocking scheme is enabled via a combination of block lock bits. the block lock bits gate program and erase operations. using the set block lock bits command, individual block lock bits can be set. this command is invalid when the ism is running or when the device is suspended. set block lock bits commands are executed by a two- cycle sequence. the set block lock bits setup, along with appropriate block address, is followed by the set block lock bits confirm and an address within the block to be locked. the ism then controls the set lock bit algorithm. when the sequence is written, the device automatically outputs status register data when read (see figure 9). the cpu can detect the completion of the set block lock bit event by analyzing the sts pin output or status register bit sr7. upon completion of set block lock bits operation, status register bit sr4 should be checked for error. if an error is detected, the status register should be cleared. the cel remains in read status register mode until a new command is is- sued. this two-step sequence of setup followed by ex- ecution ensures that lock bits are not accidentally set. an invalid set block lock bits command results in status register bits sr4 and sr5 being set to ?1.? also, reliable operation occurs only when v cc and v pen are valid. when v pen v penlk , lock bit contents are protected against any data change. clear block lock bits command the clear block lock bits command can clear all set block lock bits in parallel. this command is in- valid when the ism is running or the device is sus- pended. the clear block lock bits command is executed by a two-cycle sequence. first, a clear block lock bits setup is written, followed by a clear block lock bits confirm command. then the device au- tomatically outputs status register data when read (see figure 9). the cpu can detect completion of the clear block lock bits event by analyzing the sts pin output or the status register bit sr7. when the operation is com- pleted, status register bit sr5 should be checked. if a clear block lock bits error is detected, the status register should be cleared. the cel remains in read status reg- ister mode until another command is issued. this two-step setup sequence ensures that block lock bits are not accidentally cleared. an invalid clear block lock bits command sequence results in status register bits sr4 and sr5 being set to ?1.? also, a reli- able clear block lock bits operation can only oc- cur when v cc and v pen are valid. if a clear block dq1?dq0 = sts configuration codes notes 00 = default, ry/by# level mode used to control hold to a memory controller to prevent accessing (device ready) indication a flash memory subsystem while any flash device?s ism is busy. 01 = pulse on erase complete used to generate a system interrupt pulse when any flash device in an array has completed a block erase or sequence of queued block erases; helpful for reformatting blocks after file system free space reclamation or ?cleanup.? 10 = pulse on program complete used to generate a system interrupt pulse when any flash device in an array has completed a program operation. provides highest performance for enabling continuous buffer write operations. 11 = pulse on erase or program used to generate system interrupts to trigger enabling of flash complete arrays when either erase or program operations are completed and a common interrupt service routine is desired. table 18 configuration coding definitions 1 dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 reserved pulse on pulse on program erase complete 2 complete 2 note: 1. an invalid configuration code will result in both sr4 and sr5 being set. 2. when the device is configured in one of the pulse modes, the sts pin pulses low with a typical pulse width of 250ns.
26 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory lock bits operation is attempted when v pen v penlk , sr3 and sr5 are set to ?1.? if a clear block lock bits operation is aborted due to v pen or v cc transitioning out of valid range, block lock bit values are left in an undetermined state. to initialize block lock bit con- tents to known values, a repeat of clear block lock bits is required. protection register program command the 3v q-flash memory includes a 128-bit protec- tion register to increase the security of a system design. for example, the number contained in the protection register can be used for the flash component to com- municate with other system components, such as the cpu or asic, to prevent device substitution. the 128 bits of the protection register are divided into two 64- bit segments. one of the segments is programmed at the micron factory with a unique and unchangeable 64-bit number. the other segment is left blank for customers to program as needed. after the customer segment is programmed, it can be locked to prevent reprogramming. reading the protection register the protection register is read in the identification read mode. the device is switched to identification read mode by writing the read identifier command (90h). when in this mode, read cycles from addresses shown in table 19 or table 20 retrieve the specified information. to return to read array mode, the read array command (ffh) must be written. programming the protection register the protection register bits are programmed with two-cycle protection program commands. the 64-bit number is programmed 16 bits at a time for word-wide parts and eight bits at a time for byte- wide parts. first, the protection program setup command, c0h, is written. the next write to the device latches in addresses and data, and programs the speci- fied location. the allowable addresses are shown in table 19 and table 20. any attempt to address pro- tection program commands outside the defined protection register address space results in a status register error (program error bit sr4 is set to ?1?). at- tempting to program a locked protection register seg- ment results in a status register error (program error bit sr4 and lock error bit sr1 are set to ?1?). locking the protection register by programming bit 1 of the pr-lock location to ?0,? the user-programmable segment of the protection register is lockable. to protect the unique device num- ber, bit 0 of this location is programmed to ?0? at the micron factory. bit 1 is set using the protection pro- gram command to program ?fffdh? to the pr-lock location. when these bits have been programmed, no further changes can be made to the values stored in the protection register. protection program com- mands to a locked section will result in a status register error (program error bit sr4 and lock error bit sr1 are set to ?1?). note that the protection register lockout state is not reversible. figure 3 protection register memory map note: a0 is not used in x16 mode when accessing the protection register map (see table 19 for x16 addressing). a0 is used for x8 mode (see table 20 for x8 addressing). 4 words factory-programmed 4 words user-programmed 1 word lock 88h 85h 84h 81h 80h 0 word address
27 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory table 19 word-wide protection register addressing word use a8 a7 a6 a5 a4 a3 a2 a1 lock both 1 0 0 00000 0 factory 1 0 0 00001 1 factory 1 0 0 00010 2 factory 1 0 0 00011 3 factory 1 0 0 00100 4 user 1 0 0 00101 5 user 1 0 0 00110 6 user 1 0 0 00111 7 user 1 0 0 01000 note: 1. all address lines not specified in the above tables must be ?0? when accessing the protection register (i.e., a22?a9 = 0). table 20 byte-wide protection register addressing byte use a8 a7 a6 a5 a4 a3 a2 a1 a0 lock both 100000000 0 factory 100000010 1 factory 100000011 2 factory 100000100 3 factory 100000101 4 factory 100000110 5 factory 100000111 6 factory 100001000 7 factory 100001001 8 user 100001010 9 user 100001011 a user 100001100 b user 100001101 c user 100001110 d user 100001111 e user 100010000 f user 100010001
28 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory write word or byte count n, block address write buffer data, start address x = 0 write next buffer data, device address abort write-to-buffer command? check x = n? another write-to-buffer ? read status register sr7 = read extended status register xsr7 = 1 no yes no no 1 write to buffer aborted yes no yes yes full status check if desired issue write-to-buffer command e8h, block address write to another block address write-to- buffer timeout? 0 set timeout issue read status command yes 0 1 start programming complete x = x + 1 program buffer to flash confirm d0h figure 4 write-to-buffer flowchart bus operation command comments write write-to- data = e8h buffer block address read xsr7 = v alid addr = block address standby check xsr7 1 = write buffer available 0 = write buffer not available write 1, 2 data = n = word/byte count n = 0 corresponds to count = 1 addr = block address write 3, 4 data = write buffer data addr = device start address write 5, 6 data = write buffer data addr = device address write progr am data = d0h buffer to addr = block address flash confirm read 7 status register data with the device enabled, oe# low updates sr addr = block address standby check sr7 1 = ism ready 0 = ism busy full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode. note: 1. byte or word count values on dq0?dq7 are loaded into the count register. count ranges on this device for byte mode are n = 00h to 1fh and for word mode are n = 0000h to 000fh. 2. the device now outputs the status register when read (xsr is no longer available). 3. write buffer contents will be programmed at the device start address or destination flash address. 4. align the start address on a write buffer boundary for maximum programming performance (i.e., a4?a0 of the start address = 0). 5. the device aborts the write-to-buffer command if the current address is outside of the original block address. 6. the status register indicates an ?improper command sequence? if the write-to-buffer command is aborted. follow this with a clear status register command. 7. toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command.
29 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory 1 0 0 1 0 1 0 1 full status check if desired sr7 = start byte/word program successful device protect error voltage range error programming error full status check procedure read status register sr3 = byte/word program complete read status register data (see above) sr1 = sr4 = write 40h, address write data and address figure 5 byte/word program flowchart bus operation command comments write setup byte/ data = 40h word addr = location to be program programmed write byte/ data = data to be word programmed program addr = location to be programmed read status register data standby check sr7 1 = ism ready 0 = ism busy toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent programming operations. after each program operation or after a sequence of programming operations, an sr full status check can be done. write ffh after the last program operation to place the device in read array mode. bus operation command comments standby check sr3 1 = programming to voltage error detect standby check sr1 1 = device protect detect rp# = v ih , block lock bit is set only required for systems implemeting lock bit configuration standby check sr4 1 = programming error toggling oe# (low to high to low) updates the status register. this can be done in place of issuing the read status register command. repeat for subsequent programming operations. sr4, sr3, and sr1 are only cleared by the clear status register command in cases where multiple locations are programmed before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery.
30 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 6 program suspend/resume flowchart 1 0 sr7 = 1 0 sr2 = 1 no yes done reading write ffh start read status register programming resumed programming completed write b0h write d0h read data array write ffh read data array bus operation command comments write program data = b0h suspend addr = x read status register data addr = x standby check sr7 1 = ism ready 0 = ism busy standby check sr6 1 = programming suspended 0 = programming completed write read data = ffh array addr = x read read array locations other than that being programmed write program data = d0h resume addr = x
31 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 7 block erase flowchart 1 no no yes sr7 = suspend erase suspend erase loop full status check if desired start write confirm d0h block address read status register erase flash block(s) complete issue single block erase command 20h, block address bus operation command comments write erase data = 20h block addr = block address write erase data = d0h confirmed addr = block address read status register data with the device enabled; oe# low updates sr addr = x standby check sr7 1 = ism ready 0 = ism busy the erase confirm byte must follow erase setup. this device does not support erase queuing. full status check can be done after all erase and write sequences complete. write ffh after the last operation to reset the device to read array mode.
32 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 8 block erase suspend/resume flowchart 1 0 sr7 = 1 0 sr6 = read or program? read program no yes done? start read status register block erase resumed block erase completed write b0h write d0h read data array write ffh read array data program loop bus operation command comments write erase data = b0h suspend addr = x read status register data addr = x standby check sr7 1 = ism ready 0 = ism busy standby check sr6 1 = block erase suspended 0 = block erase completed write erase data = d0h resume addr = x
33 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 9 set block lock bits flowchart 1 0 0 1 0 1 0 1 full status check if desired sr7 = start set block lock bits successful command sequence error voltage range error set block lock bits error full status check procedure read status register sr3 = set block lock bits complete read status register data (see above) sr4,5 = sr4 = write 60h, block address write 01h, block address bus operation command comments write set b lock data = 60h lock bits addr = block address setup write set b lock data = 01h lock bits addr = block address confirm read status register data standby check sr7 1 = ism ready 0 = ism busy repeat for subsequent lock bit operations. full status check can be done after each lock bit set operation or after a sequence of lock bit set operations write ffh after the last lock bit set operation to place device in read array mode. bus operation command comments standby check sr3 1 = programming voltage error detect standby check sr4, sr5 both 1 = command sequence error standby check sr4 1 = set block lock bits error sr5, sr4, and sr3 are only cleared by the clear status register command in cases where multiple lock bits are set before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery.
34 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 10 clear block lock bits flowchart 1 0 0 1 0 1 0 1 full status check if desired sr7 = start clear block lock bits successful command sequence error clear block lock bits error voltage range error full status check procedure read status register sr3 = clear block lock bits complete read status register data (see above) sr4,5 = sr5 = write 60h write d0h bus operation command comments write clear data = 60h block lock addr = x bits setup write clear block data = d0h lock bits addr = x or confirm read status register data standby check sr7 1 = ism ready 0 = ism busy write ffh after the clear block lock bits operation to place device in read array mode. bus operation command comments standby check sr3 1 = programming voltage error detect standby check sr4, 5 both 1 = command sequence error standby check sr5 1 = clear block lock bits error sr5, sr4, and sr3 are only cleared by the clear status register command. if an error is detected, clear the status register before attempting retry or other error recovery.
35 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 11 protection register programming flowchart yes no 1, 1 0, 1 1, 1 full status check if desired sr7 = 1 start program successful protection register programming error attempted program to locked register ? aborted v pen range error full status check procedure read status register sr3, sr4 = program complete read status register data (see above) sr1, sr4 = sr1, sr4 = write c0h (protection register program setup) write protect register address/data bus operation command comments write protection data = c0h program setup write protection data = data to program program addr = location to program read status register data toggle ce# or oe# to update status register data standby check sr7 1 = ism ready 0 = ism busy protection program operations can only be addressed within the protection register address space. addresses outside the defined space will return an error. repeat for subsequent programming operations. sr full status check can be done after each program or after a sequence of program operations. write ffh after the last program operation to reset device to read array mode. bus comments operation command sr1 sr3 sr4 standby 0 1 1 v pen low standby 0 0 1 protection register program error standby 1 0 1 register locked: aborted sr3, if set during a program attempt, must be cleared before further attempts are allowed by the ism. sr1, sr3, and sr4 are only cleared by the clear staus register command, in cases of multiple protection register program operations, before full status is checked. if an error is detected, clear the status register before attempting retry or other error recovery.
36 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory design considerations five-line output control micron provides five control inputs (ce0, ce1, ce2, oe#, and rp#) to accommodate multiple memory con- nections in large memory arrays. this control provides the lowest possible memory power dissipation and en- sures that data bus contention does not occur. to efficiently use these control inputs, an address decoder should enable the device (see table 2) while oe# is connected to all memory devices and the system?s read# control line. this ensures that only selected memory devices have active outputs while deselected memory devices are in standby mode. dur- ing system power transitions, rp# should be connected to the system powergood signal to prevent unin- tended writes. powergood should also toggle dur- ing system reset. sts and block erase, program, and lock bit configuration polling as an open drain output, sts should be connected to v cc q by a pull-up resistor to provide a hardware method of detecting block erase, program, and lock bit configuration completion. it is recommended that a 2.5k ? resistor be used between sts# and v cc q. in de- fault mode, it transitions low after block erase, pro- gram, or lock bit configuration commands and returns to high-z when the ism has finished executing the internal algorithm. see the configuration com- mand for alternate configurations of the sts pin. sts can be connected to an interrupt input of the system cpu or controller. sts is active at all times. in default mode, it is also high-z when the device is in block erase suspend (with programming inactive), program sus- pend, or reset/power-down mode. power supply decoupling device decoupling is required for flash memory power switching characteristics. there are three sup- ply current issues to consider: standby current levels, active current levels, and transient peaks produced by falling and rising edges of cex and oe#. transient cur- rent magnitudes depend on the device outputs? ca- pacitive and inductive loading. two-line control and proper decoupling capacitor selection suppresses tran- sient voltage peaks. because micron q-flash memory devices draw their power from three v cc pins (these devices do not include a v pp pin), it is recommended that systems without separate power and ground planes attach a 0.1f ceramic capacitor between each of the device?s three v cc pins (this includes v cc q) and gnd. these high-frequency, low-inductance capaci- tors should be placed as close as possible to package leads on each micron q-flash memory device. addi- tionally, for every eight devices, a 4.7f electrolytic capacitor should be placed between v cc and gnd at the array?s power supply connection.
37 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory reducing overshoots and under- shoots when using buffers or transceivers overshoots and undershoots can sometimes cause input signals to exceed flash memory specifications as faster, high-drive devices such as transceivers or buff- ers drive input signals to flash memory devices. many buffer/transceiver vendors now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs. internal output-damping resistors diminish the nominal output drive currents, while still leaving sufficient drive capability for most applications. these internal output-damping resistors help reduce unnecessary overshoots and undershoots by diminishing output-drive currents. when consider- ing a buffer/transceiver interface design to flash, de- vices with internal output-damping resistors or re- duced-drive outputs should be used to minimize over- shoots and undershoots. v cc , v pen , rp# transitions if v pen or v cc falls outside of the specified operating ranges, or rp# is not set to v ih , block erase, program, and lock bit configuration are not guaranteed. if rp# transitions to v il during block erase, program, or lock bit configuration, sts (in default mode) will remain low for a maximum time of t plph + t phrh, until the reset operation is complete and the device enters reset/power-down mode. the aborted operation may leave data partially corrupted after programming, or partially altered after an erase or lock bit configuration. therefore, block erase and lock bit configura- tion commands must be repeated after normal op- eration is restored. device power-off or rp# = v il clears the status register. the cel latches commands issued by system software and is not altered by v pen or cex transitions, or ism actions. its state is read array mode upon power-up, upon exiting reset/power-down mode, or after v cc transitions below v lko . v cc must be kept at or above v pen during v cc transitions. after block erase, program, or lock bit configuration, and after v pen transitions to v penlk , the cel must be placed in read array mode via the read array com- mand if subsequent access to the memory array is de- sired. during v pen transitions, v pen must be kept at or below v cc . power-up/down protection during power transition, the device itself provides protection against accidental block erasure, program- ming, or lock bit configuration. internal circuitry resets the cel to read array mode at power-up. a system designer must watch out for spurious writes for v cc voltages above v lko when v pen is active. because we# must be low and the device enabled (see table 2) for a command write, driving we# to v ih or disabling the device inhibits writes. the cel?s two-step command sequence architecture provides added protection against data alteration. in-system block lock and un- lock capability protects the device against inadvertent programming. the device is disabled when rp# = v il regardless of its control inputs. keeping v pen below v penlk prevents inadvertent data change. power dissipation designers must consider battery power consump- tion not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed.
38 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory absolute maximum ratings* temperature under bias expanded ................................... ?40oc to +85oc storage temperature ........................... ?65oc to +125oc for v cc q = +2.7v to +3.6v voltage on any pin ........................ ?2.0v to +5.0v** for v cc q = +4.5v to +5.5v all pins except v cc .......................... ?2.0v to +7.0v** v cc ..................................................... ?2.0v to +5.5v** output short circuit current ............................. 100ma ? *stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. **all specified voltages are with respect to gnd. mini- mum dc voltage is ?0.5v on input/output pins and -0.2v on v cc and v pen pins. during transitions, this level may undershoot to ?2.0v for periods <20ns. maximum dc voltage on input/output pins, v cc , and v pen is v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. ?output shorted for no more than one second. no more than one output shorted at a time.
39 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory note: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). 2. sampled, not 100% tested. 3. includes sts. 4. mt28f320j3rg-11 f and mt28f640j3rg-12 f only. temperature and recommended dc operating conditions commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) parameter symbol min max units notes v cc supply voltage (2.7v?3.6v) v cc 1 2.7 3.6 v v cc q supply voltage (2.7v?3.6v) v cc q1 2.7 3.6 v v cc q supply voltage (4.5v?5.5v) v cc q2 4.5 5.5 v input and v pen load current v cc = v cc (max); v cc q = v cc q (max) i li 1 a 1 v in = v cc q or gnd output leakage current v cc = v cc (max); v cc q = v cc q (max) i lo 10 a 1 v in = v cc q or gnd input low voltage v il -0.5 0.8 v 2 input high voltage v ih 2v cc q + 0.5 v 2 output low voltage (2.7v?3.6v) v cc q = v cc q1 (min) v ol 0.4 v 2, 3 i ol = 2ma v cc q = v cc q1 (min) 0.2 v i ol = 100a output low voltage (4.5v?5.5v) v cc q = v cc q2 (min) v ol 0.45 v 4 i ol = 2ma output low voltage (4.5v?5.5v) v cc q = v cc q2 (min) 0.25 v 4 i ol = 100a output high voltage (2.7v?3.6v) v cc q = v cc q (min) v oh 0.85 v cc q v2 i oh = -2.5ma v cc q = v cc q (min) v cc q - 0.2 v i oh = -100a output high voltage (4.5v?5.5v) v cc q = v cc q2 (min) v oh 2.4 v4 i oh = -2.5ma v cc q = v cc q2 (min) v cc q - 0.2 v i oh = -100a
40 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory recommended dc electrical characteristics commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) description conditions symbol typ max units notes v cc standby cmos inputs; v cc = v cc (max); i cc 1 50 120 a 1, 2, 3 current device is enabled; rp# = v cc q 0.2v ttl inputs; v cc = v cc (max); 0.71 2 ma device is enabled; rp# = v ih v cc power-down rp# = gnd 0.2v; i cc 2 50 120 a current i out (sts) = 0ma v cc page mode cmos inputs; v cc = v cc (max); i cc 3 11 20 ma 1, 3 read current v cc q = v cc q (max) using standard 4-word page mode reads; device is enabled; f = 5 mhz; i out = 0ma cmos inputs; v cc = v cc (max); 15 29 ma v cc q = v cc q (max) using standard 4-word page mode reads; device is enabled; f = 33 mhz; i out = 0ma v cc asynchronous mode cmos inputs; v cc = v cc (max); i cc 4 12.5 50 ma 1, 3 read current v cc q = v cc q (max) using standard w ord/byte single reads; device is enabled; f = 5 mhz; i out = 0ma note: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). 2. includes sts. 3. cmos inputs are either v cc 0.2v or v ss 0.2v. ttl inputs are either v il or v ih . 4. sampled, not 100% tested. 5. i ccws and i cces are specified with the device deselected. if the device is read or written while in erase suspend mode, the device?s current draw is i ccr or i ccw . 6. block erase, programming, and lock bit configurations are inhibited when v pen v penlk , and they are not guaranteed in the range between v penlk (max) and v penh (min), or above v penh (max). 7. typically, v pen is connected to v cc . 8. block erase, programming, and lock bit configurations are inhibited when v cc < v lko , and they are not guaranteed in the range between v lko (min) and v cc (min), or above v cc (max). (continued on next page) capacitance (t a = +25oc; f = 1 mhz) parameter/condition symbol typ max units input capacitance c 5 8 p f output capacitance byte# c out 10 12 p f all other pins c out 512pf
41 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory recommended dc electrical characteristics (continued) commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) description conditions symbol typ max units notes v cc program or set cmos inputs, v pen = v cc i cc 5 22 60 ma 1, 4 lock bits current ttl inputs, v pen = v cc 24 70 ma v cc block erase or clear cmos inputs, v pen = v cc i cc 6 20 70 ma 1, 4 block lock bits current ttl inputs, v pen = v cc 22 80 ma v cc program suspend or device is disabled i cc 7 10 ma 1 block erase suspend current v pen lockout during v penlk 1 v 5, 6, 7 program, erase, and lock bit operations v pen during block erase, v penh 2.7 3.6 v 6, 7 program, or lock bit operations v cc lockout voltage v lko 2.2 v 8 note: 1. all currents are in rms unless otherwise noted. these currents are valid for all product versions (packages and speeds). 2. includes sts. 3. cmos inputs are either v cc 0.2v or v ss 0.2v. ttl inputs are either v il or v ih . 4. sampled, not 100% tested. 5. i ccws and i cces are specified with the device deselected. if the device is read or written while in erase suspend mode, the device?s current draw is i ccr or i ccw . 6. block erase, programming, and lock bit configurations are inhibited when v pen v penlk , and they are not guaranteed in the range between v penlk (max) and v penh (min), or above v penh (max). 7. typically, v pen is connected to v cc . 8. block erase, programming, and lock bit configurations are inhibited when v cc < v lko , and they are not guaranteed in the range between v lko (min) and v cc (min), or above v cc (max).
42 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory figure 13 transient equivalent testing load circuit figure 12 transient input/output reference waveform for v cc q = 2.7v?3.6v, or v cc q = 4.5v?5.5v test points input v cc q/2 v cc q/2 output v cc q 0.0 note: ac test inputs are driven at v cc q for a logic 1 and 0.0v for a logic 0. input timing begins, and output timing ends, at v cc q/ 2v (50% of v cc q). input rise and fall times (10% to 90%) < 5ns. device under test out r l = 3.3k ? 1.3v 1n914 c l note: c l includes jig capacitance test configuration capacitance loading value test configuration c l (pf) v cc q = v cc = 2.7v to 3.6v 30 30 v cc q = 4.5v to 5.5v 30
43 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory ac characteristics ? read-only operations (notes: 1, 2, 4); commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) v cc = 2.7v?3.6v v cc q = 2.7v?3.6v or 4.5v?5.5v parameter symbol density min max units notes read/write cycle time t rc 32mb 110 ns 64mb 120 ns 128mb 150 ns address to output delay t aa 32mb 110 ns 64mb 120 ns 128mb 150 ns cex to output delay t ace 32mb 110 ns 64mb 120 ns 128mb 150 ns oe# to non-array output delay t aoe all 50 ns 3, 5 oe# to array output delay t aoa all 25 ns 5 rp# high to output delay t rwh 32mb 150 ns 64mb 180 ns 128mb 210 ns cex to output in low-z t oec all 0 ns 6 oe# to output in low-z t oeo all 0 ns 6 cex high to output in high-z t odc all 35 ns 6 oe# high to output in high-z t odo all 15 ns 6 output hold from address, cex, or oe# t oh all 0 ns 6 change, whichever occurs first cex low to byte# high or low t cb all 10 ns 6 byte# to output delay t aby all 1,000 ns byte# to output in high-z t odb all 1,000 ns 6 cex high to cex low t cwh all 0 ns 6 page address access time t apa all 25 ns 6 note: 1. cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). 2. see ac input/output reference waveforms for the maximum allowable input slew rate. 3. oe# may be delayed up to t ace - t aoe after the first edge of cex that enables the device (see table 2) without impact on t ace . 4. see figures 12 and 13, transient input/output reference waveform for v cc q = 2.7v?3.6v or v cc q = 4.5v?5.5v, and transient equivalent testing load circuit for testing characteristics. 5. when reading the flash array, a faster t aoe applies. nonarray reads refer to status register reads, query reads, or device identifier reads. 6. sampled, not 100% tested.
44 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory page mode and standard word/byte read operations note: cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined as the first edge of ce0, ce1, or ce2 that disables the device. disabled cex enabled addresses (a2?a0) oe# dq0?dq15 we# rp# v ih v il v ih v il v ih v il v il v ih v il v ih v il v ih v il v oh v ol valid address valid address valid address t rc valid address byte v ih t cwh t aa t ace t aoe/ t aoa t oeo t odb t rwh t oec t cb t aby t odc t odo v cc addresses (a22?a3) v ih v il t oh t apa undefined valid output valid output valid output valid output high-z high-z timing parameters v cc = 2.7v?3.6v v cc q = 2.7v?3.6v or 4.5v?5.5v symbol min max units t rc (32mb) 110 ns t rc (64mb) 120 ns t rc (128mb) 150 ns t aa (32mb) 110 ns t aa (64mb) 120 ns t aa (128mb) 150 ns t ace (32mb) 110 ns t ace (64mb) 120 ns t ace (128mb) 150 ns t aoe 50 ns t aoa 25 ns t rwh (32mb) 150 ns v cc = 2.7v?3.6v v cc q = 2.7v?3.6v or 4.5v?5.5v symbol min max units t rwh (64mb) 180 ns t rwh (128mb) 210 ns t oec 0 ns t oeo 0 ns t odc 35 ns t odo 15 ns t oh 0 ns t cb 10 ns t aby 1,000 ns t odb 1,000 ns t cwh 0 ns t apa 25 ns
45 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory note: 1. cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined as the first edge of ce0, ce1, or ce2 that disables the device. 2. read timing characteristics during block erase, program, and lock bit configuration operations are the same as during read-only operations. refer to ac characteristics ? read-only operations. 3. a write operation can be initiated and terminated with either cex or we#. 4. sampled, not 100% tested. 5. write pulse width ( t wp) is defined from cex or we# going low (whichever goes low last) to cex or we# going high (whichever goes high first). 6. refer to table 4 for valid a in and d in for block erase, program, or lock bit configuration. 7. write pulse width high ( t wph) is defined from cex or we# going high (whichever goes high first) to cex or we# going low (whichever goes low first). 8. for array access, t aa is required in addition to t wr for any accesses after a write. 9. sts timings are based on sts configured in its ry/by# default mode. 10. v pen should be held at v penh until determination of block erase, program, or lock bit configuration success (sr1/3/4/5 = 0). ac characteristics ? write operations (notes: 1, 2, 3); commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) ac characteristics -11/-12/-15 parameter symbol min max units notes rp# high recovery to we# (cex) going low t rs 1 s 4 cex (we#) low to we# (cex) going low t cs ( t ws) 0 ns 5 write pulse width t wp ( t cp) 70 ns 5 data setup to we# (cex) going high t ds 50 ns 6 address setup to we# (cex) going high t as 55 ns 6 cex (we#) hold from we# (cex) high t ch ( t wh) 0 ns data hold from we# (cex) high t dh 0 ns address hold from we# (cex) high t ah 0 ns write pulse width high t wph ( t cph) 30 ns 7 v pen setup to we# (cex) going high t vps 0 ns 4 write recovery before read t wr 35 ns 8 we# (cex) high to sts going low t sts 200 ns 9 v pen hold from valid srd, sts going high t vph 0 ns 4, 9, 10 we# (cex) high to status register busy t wb 200 ns 4
46 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory block erase, program, and lock bit configuration performance (notes: 1, 2, 3); commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) characteristics -11/-12/-15 parameter symbol typ max 8 units notes write buffer byte program time t wed1 150 654 s 4, 5, 6, 7 (time to program 32 bytes/16 words) byte/word program time (using word/byte program command) t wed2 14 630 s 4 block program time (using write-to-buffer command) t wed3 0.6 1.7 sec 4 block erase time t wed4 0.75 5 sec 4 set lock bits time t wed5 64 75 s 4 clear block lock bits time t wed6 0.5 0.7 sec 5 program suspend latency time to read t lps 25 30 s erase suspend latency time to read t les 26 35 s note: 1. typical values measured at t a = +25oc and nominal voltages. assumes corresponding lock bits are not set. subject to change based on device characterization. 2. these performance numbers are valid for all speed versions. 3. sampled, but not 100% tested. 4. excludes system-level overhead. 5. these values are valid when the buffer is full, and the start address is aligned on a 32-byte boundary. 6. effective per-byte program time is 4.7s/byte (typical). 7. effective per-word program time is 9.4s/word (typical). 8. max values are measured at worst-case temperature and v cc corner after 100,000 cycles.
47 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory t ah 0 ns t wph 30 ns t vps 0 ns t wr 35 ns t sts 200 ns t vph 0 ns t wb 200 ns write operations 1 note: 1. cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). sts is shown in its default mode (ry/by#). 2. v cc power-up and standby. 3. write block erase, write buffer, or program setup. 4. write block erase or write buffer confirm, or valid address and data. 5. automated erase delay. 6. read status register or query data. 7. write read array command. disabled cex (we#) enabled addresses oe# dq0?dq15 undefined disabled we# (cex) enabled v ih v il a in v pen rp# v ih v il v penlk v penh v ih v il v ih v il v ih v il v ih v il a in d in d in t as note 3 note 2 note 4 note 5 note 6 note 7 t rs t ch t wr t ah t cs t wph t wp t sts t ds t dh t wb v il sts v oh v ol valid ready srd valid busy srd d in t vps t vph -11/-12/-15 symbol min max units timing parameters -11/-12/-15 symbol min max units t rs 1 s t cs 0 ns t wp 70 ns t ds 50 ns t as 55 ns t ch 0 ns t dh 0 ns
48 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory t dh 0 ns t ah 0 ns t sts 200 ns t weh 200 ns resume operations 1 note: 1. cex low is defined as the first edge of ce0, ce1, or ce2 that enables the device. cex high is defined at the first edge of ce0, ce1, or ce2 that disables the device (see table 2). sts is shown in its default mode (ry/by#). 2. erase resume, or program resume. 3. read status, erase suspend or program suspend. 4. sts value will be: v ih after erase suspend and program suspend commands v il after read status command command disabled cex (we#) enabled addresses oe# dq0?dq15 undefined disabled we# (cex) enabled v ih v il a in v pen rp# v ih v il v penlk v penh v ih v il v ih v il v ih v il v ih v il a in t as note 2 note 3 note 4 t ch t ah t cs t wp t weh t sts t ds t dh v il sts v oh v ol t sts command ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) -11/-12/-15 symbol min max units timing parameters -11/-12/-15 symbol min max units t cs 0 ns t wp 70 ns t ds 50 ns t as 55 ns t ch 0 ns
49 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory reset operation 4 note: 1. sts is shown in its default mode (ry/by#). 2. these specifications are valid for all product versions (packages and speeds). 3. if rp# is asserted while a block erase, program, or lock bit configuration operation is not executing, then the minimum required rp# pulse low time is 100ns. 4. a reset time, t phqv, is required from the latter of sts (in ry/by# mode) or rp# going high until outputs are valid. rp# v ih v il sts v ih v il t phrh t plph reset specifications (note: 1); commercial temperature (0oc t a +85oc), extended temperature (-40oc t a +85oc) characteristics -11/-12/-15 parameter symbol min max units notes rp# pulse low time t plph 35 s 2 (if rp# is tied to v cc , this specification is not applicable) rp# high to reset during block erase, program, or t phrh 100 ns 3 lock bit configuration
50 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory note: 1. all dimensions in millimeters. 2. package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. see detail a 0.50 typ 14.00 0.08 0.25 1.20 max 18.40 0.08 20.00 0.10 detail a 0.5 0.10 0.80 typ 0.10 +0.10 -0.05 0.10 0.25 plane gage 0.15 +0.03 -0.02 pin #1 index plastic package material: epoxy novolac lead finish: tin/lead plate package width and length do not include mold protrusion. allowable protrusion is 0.25 per side 56-pin tsop type i
51 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory note: 1. all dimensions in millimeters. 64-ball fbga 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron, the micron and m logos and q-flash are trademarks and/or servicemarks of micron technology, inc. data sheet designations preliminary: this data sheet contains initial characterization limits that are subject to change upon full characterization of production devices. this designation applies to the mt28f320j3 and MT28F128J3 devices. no marking: this data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. this designation applies to the mt28f640j3 device. 0.08 c seating plane c 0.850 0.075 64x ? 0.45 ball a8 7.00 0.05 3.50 0.05 3.50 0.05 5.50 0.05 13.00 0.10 6.50 0.05 ball a1 id ball a1 id 1.20 max ball a1 1.00 typ 1.00 typ 7.00 10.00 0.10 mold compound: epoxy novolac substrate: plastic laminate solder ball material: eutectic 63% sn, 37% pb or 62% sn, 36% pb, 2%ag solder ball pad: ? .33mm solder ball diameter refers to post reflow condition. the pre- reflow diameter is ? 0.40 c l c l
52 128mb, 64mb, 32mb q-flash memory micron technology, inc., reserves the right to change products or specifications without notice. mt28f640j3_7.p65 ? rev. 6, pub. 8/02 ?2002, micron technology, inc. 128mb, 64mb, 32mb q-flash memory revision history rev. 6 ............................................................................................................................... .......................................................... 8/02 added commercial temperature range updated configuration coding definitions table removed 3.0v?3.6v v cc q voltage range option updated v lko , v penlk , t aoa, t odc, t apa, t ch ( t wh), t sts, and t wb added resume operations timing diagram rev. 5 ............................................................................................................................... .......................................................... 5/02 updated mt28f320j3 information rev. 4 ............................................................................................................................... .......................................................... 2/02 added v cc q = 4.5v?5.5v parameter for 32mb and 64mb devices updated erase and program timing parameters removed block erase status bit rev. 3 ............................................................................................................................... .......................................................... 6/01 updated package drawing and corresponding notes rev. 2 ............................................................................................................................... .......................................................... 5/01 added 128mb device information added 64-ball fbga (1.0mm pitch) package original document, rev. 1 ............................................................................................................................... ................... 12/00

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